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IDTCSPUA877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
FEATURES: DESCRIPTION:
IDTCSPUA877A
* 1 to 10 differential clock distribution * Optimized for clock distribution in DDR2 (Double Data Rate) SDRAM applications * Operating frequency: 125MHz to 410MHz * Stabilization time: <6us * Very low skew: 40ps * Very low jitter: 40ps * 1.8V AVDD and 1.8V VDDQ * CMOS control signal input * Test mode enables buffers while disabling PLL * Low current power-down mode * Tolerant of Spread Spectrum input clock * Available in 52-Ball VFBGA and 40-pin VFQFPN packages
APPLICATIONS:
* Meets or exceeds JEDEC standard CUA877 for registered DDR2 clock driver * Along with SSTUA32864/66, DDR2 register, provides complete solution for DDR2 DIMMs
The CSPUA877A is a PLL based clock driver that acts as a zero delay buffer to distribute one differential clock input pair(CLK, CLK ) to 10 differential output pairs (Y [0:9], Y [0:9]) and one differential pair of feedback clock output (FBOUT, FBOUT). External feedback pins (FBIN, FBIN) for synchronization of the outputs to the input reference is provided. OE, OS, and AVDD control the power-down and test mode logic. When AVDD is grounded, the PLL is turned off and bypassed for test mode purposes. When the differential clock inputs (CLK, CLK) are both at logic low, this device will enter a low power-down mode. In this mode, the receivers are disabled, the PLL is turned off, and the output clock drivers are disabled, resulting in a clock driver current consumption of less than 500A. The CSPUA877A requires no external components and has been optimised for very low phase error, skew, and jitter, while maintaining frequency and duty cycle over the operating voltage and temperature range. The CSPUA877 , designed for use in both module assemblies and system motherboard based solutions, provides an optimum high-performance clock source. The CSPUA877A is available in Commercial Temperature Range (0C to +70C). See Ordering Information for details.
FUNCTIONAL BLOCK DIAGRAM
OE OS AVDD LD or OE POWER DOWN AND LD, OS, or OE TEST MODE PLL BYPASS LOGIC LD
Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4
CLK CLK 10K - 100K FBIN FBIN PLL
Y5 Y5 Y6 Y6 Y7 Y7 Y8 Y8 Y9
NOTE: The Logic Detect (LD) powers down the device when a logic LOW is applied to both CLK and CLK.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Y9 FBOUT
COMMERCIAL TEMPERATURE RANGE
1
c 2006 Integrated Device Technology, Inc.
FBOUT
OCTOBER 2006
DSC 6872/4
IDTCSPUA877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
6
Y6 Y5 Y5
Y6 GND GND
Y7 GND NB NB GND Y2
C
Y7 OS VDDQ
FBIN VDDQ NB NB
FBIN FBOUT FBOUT OE NB NB GND NB NB GND
Y8
Y8 Y9 Y9
5
VDDQ VDDQ
GND GND
4
3
Y0 Y0 Y1
A
GND GND Y1
B
VDDQ
VDDQ VDDQ
GND GND Y3
J
Y4 Y4 Y3
K
2
VDDQ VDDQ VDDQ Y2
D
1
CLK
E
CLK
F
AGND AVDD
G H
VFBGA TOP VIEW
52 BALL VFBGA PACKAGE LAYOUT
0.65mm
6 5 4 3 2 1 A B C D E F G H J K
TOP VIEW
A 1 2 3 4 5 6
B
C
D
E
F
G
H
J
K
2
IDTCSPUA877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION, CONT.
VDDQ VDDQ
ABSOLUTE MAXIMUM RATINGS(1,2)
Symbol VDDQ, AVDD VI(3) VO(3) IIK (VI <0) IOK (VO <0 or VO > VDDQ) IO (VO =0 to VDDQ) VDDQ or GND TSTG Rating Supply Voltage Range Input Voltage Range Voltage range applied to any output in the high or low state Input clamp current Output Clamp Current Max -0.5 to +2.5 -0.5 to VDDQ + 0.5 -0.5 to VDDQ + 0.5 50 50 Unit V V V mA mA
Y1
Y1
Y0
Y0
Y5
Y6
39
32
Y6
Y5
40
38
37
36
35
33
34
31
VDDQ Y2 Y2 CLK CLK VDDQ AGND AVDD VDDQ GND
1 2 3 4 5 6 7 8 9 10
11 12 13 14 15 16 17 18 19 20
30 29 28 27 26 GND 25 24 23 22 21
Y7 Y7 VDDQ FBIN FBIN FBOUT FBOUT VDDQ OE OS
Continuous Output Current Continuous Current Storage Temperature Range
50 100 - 65 to +150
mA mA C
VFQFPN TOP VIEW
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils. 3. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This value is limited to 2.5V max.
Y4
VDDQ
VDDQ
Y3
Y3
Y4
Y9
Y9
Y8
Y8
CAPACITANCE(1)
Parameter CIN CI CL Description Input Capacitance VI = VDDQ or GND Delta Input Capacitance CLK, CLK, FBIN, FBIN Load Capacitance -- 10 -- pF
NOTE: 1. Unused inputs must be held high or low to prevent them from floating.
Min. 2
Typ. --
Max. 3 0.25
Unit pF pF
RECOMMENDED OPERATING CONDITIONS
Symbol AVDD(1) VDDQ TA Supply Voltage I/O Supply Voltage Operating Free-Air Temperature 1.7 0 Parameter Min. Typ. VDDQ 1.8 1.9 +70 Max. Unit V V
C
NOTE: 1. The PLL is turned off and bypassed for test purposes when AVDD is grounded. During this test mode, VDDQ remains within the recommended operating conditions and no timing parameters are guaranteed.
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IDTCSPUA877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (VFBGA)
Pin Name AGND AVDD CLK, CLK FBIN, FBIN FBOUT, FBOUT GND VDDQ OE OS Y[0:9] Y[0:9] NB Pin Number G1 H1 E1, F1 E6, F6 G6, H6 B2 - B5, C2, C5, H2, H5, J2 - J5 D2 - D4, E2, E5, F2, G2 - G5 F5 D5 A3, A4, B1, B6, C1, C6, K1, K2, K5, K6 A1, A2, A5, A6, D1, D6, J1, J6, K3, K4 1.8V analog supply Differential clock input with a 10K to 100K pulldown resistor Feedback differential clock input Feedback differential clock output Ground 1.8V supply Output Enable Output Select (tied to GND or VDDQ) Buffered output of input clock, CLK Buffered output of input clock, CLK No Ball Description Ground for 1.8V analog supply
PIN DESCRIPTION (VFQFPN)
Pin Name AGND AVDD CLK, CLK FBIN, FBIN FBOUT, FBOUT GND VDDQ OE OS Y[0:9] Y[0:9] NB Pin Number 7 8 4, 5 26, 27 24, 25 10 1, 6, 9, 15, 20, 23, 28, 31, 36 22 21 3, 11, 14, 16, 19, 29, 33, 34, 38, 39 2, 12, 13, 17, 18, 30, 32, 35, 37, 40 1.8V analog supply Differential clock input with a 10K to 100K pulldown resistor Feedback differential clock input Feedback differential clock output Ground 1.8V supply Output Enable Output Select (tied to GND or VDDQ) Buffered output of input clock, CLK Buffered output of input clock, CLK No Ball Description Ground for 1.8V analog supply
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IDTCSPUA877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
FUNCTION TABLE(1,2)
INPUTS AVDD GND GND GND GND 1.8V (nom) 1.8V (nom) 1.8V (nom) 1.8V (nom) 1.8V (nom) X OE H H L L L L H H X X OS X X H L H L X X X X CLK L H L H L H L H L
(3)
OUTPUTS CLK H L H L H L H L L
(3)
Y L H L(z) L(z) Y7 Active L(z) L(z) Y7 Active L H L(z)
Y H L L(z) L(z) Y7 Active L(z) L(z) Y7 Active H L L(z)
FBOUT L H L H L H L H L(z)
FBOUT H L H L H L H L L(z) Reserved
PLL OFF OFF OFF OFF ON ON ON ON OFF
H
H
NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care 2. L(z) means the outputs are disabled to a LOW state, meeting the IODL limit in DC Electrical Characteristics table. 3. The device will enter a low power-down mode when CLK and CLK are both at logic LOW.
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IDTCSPUA877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0C to +70C
Symbol VIK VIL(2) VIH(2) VIN(1) VID(DC)(2) VOD(3) VOH VOL IODL IIN IDDLD IDD Parameter Input Clamp Voltage (All Inputs) Input LOW Voltage (OE, OS, CLK, CLK) Input HIGH Voltage (OE, OS, CLK, CLK) Input Signal Voltage DC Input Differential Voltage Output Differential Voltage Output HIGH Voltage Output LOW Voltage Output Disabled LOW Current Input Current CLK, CLK OE, OS, FBIN, FBIN Static Supply Current (IDDQ and IADD) Dynamic Power Supply Current (IDDQ and IADD)(4,5)
NOTES: 1. VIN specifies the allowable DC excursion of each different output. 2. VID is the magnitude of the difference between the input level on CLK and the input level on CLK. The CLK and CLK VIH and VIL limits are used to define the DC LOW and HIGH levels for the power down mode. 3. VOD is the magnitude of the difference between the true output level and the complementary level. 4. All Outputs are left open (unconnected to PCB). 5. Total IDD = IDDQ + IADD = FCK * CPD * VDDQ, for Cpd = (IDDQ + IADD) / (FCK * VDDQ) where FCK is the input frequency, VDDQ is the power supply, and CPD is the Power Dissipation Capacitance.
Conditions VDDQ = 1.7V, II = -18mA
Min. 0.65VDDQ -0.3 0.3
Typ.
Max. - 1.2 0.35VDDQ VDDQ + 0.3 VDDQ + 0.4 0.1 0.6
Unit V V V V V V V A A A mA
AVDD/VDDQ = 1.7V IOH = -100A, VDDQ = 1.7V to 1.9V IOH = -9mA, VDDQ = 1.7V IOL = 100A, VDDQ = 1.7V to 1.9V IOL = 9mA, VDDQ = 1.7V OE = L, VODL = 100mV, AVDD/VDDQ = 1.7V AVDD/VDDQ = Max., VI = 0V to VDDQ AVDD/VDDQ = Max., CLK and CLK = GND AVDD/VDDQ = Max., CLK = 410MHz
0.6 VDDQ - 0.2 1.1
100
250 10 500 300
TIMING REQUIREMENTS
Symbol fCLK tDC tL Parameter Operating Clock Frequency(1,2,5) Application Clock Frequency(1,3,5) Input Clock Duty Cycle Stabilization Time(4) Min. 125 160 40 Max. 410 410 60 6 Unit MHz MHz % s
NOTES: 1. The PLL will track a spread spectrum clock input. 2. Operating clock frequency is the range over which the PLL will lock, but may not meet all timing specifications. To be used only for low speed system debug. 3. Application clock frequency is the range over which timing specifications apply. 4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up. During normal operation, the stabilization time is also the time required for the PLL circuit to obtain phase lock of its feedback signal to its reference signal when CLK and CLK go to a logic LOW state, enters the power-down mode, and later return to active operation. CLK and CLK may be left floating after they have been driven LOW for one complete clock cycle. 5. Will lock to input frequency as low as 30MHz at room temperature and nominal or higher supply voltage (1.8V - 1.9V).
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IDTCSPUA877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS(1)
Symbol tEN tDIS sLR(I) sLR(O)(4) VOX(6) tJIT(CC+) tJIT(CC-) t()(5) t()DYN(7) tSK(O)(7) tJIT(PER)(3,7) tJIT(HPER)(3) t(SU)(7) t(H)(7) Description OE to any Y/Y OE to any Y/Y Output Enable (OE) Input Clock Slew Rate, measured single-ended Output Clock Slew Rate, measured single-ended Output Differential-Pair Cross-Voltage Cycle-to-Cycle Period Jitter Cycle-to-Cycle Period Jitter Static Phase Offset Dynamic Phase Offset Output Clock Skew Period Jitter Half-Period Jitter | tJIT(PER) | + | t()DYN | + tSK(O) | t()DYN | + tSK(O) SSC Modulation Frequency SSC Clock Input Frequency Deviation CSPUA877A PLL designs should target the value below to minimize SSC-induced skew: PLL Loop Bandwidth (-3dB from unity gain) 2 MHz
NOTES: 1. There are two different terminations that are used with the above AC tests. The output load shown in figure 1 is used to measure the input and output differential pair cross-voltage only. The output load shown in figure 2 is used to measure all other tests, including input and output slew rates. For consistency, use 50 equal length cables with SMA connectors on the test board. 2. Refers to transition of non-inverting output. 3. Period jitter and half-period jitter specifications are seperate specifications that must be met independently of each other. 4. To eliminate the impact of input slew rates on static phase offset, the input slew rates of reference clock input (CLK, CLK) and feedback clock input (FBIN, FBIN) are recommended to be nearly equal. The 2.5V/ns slew rates are shown as a recommended target. Compliance with these nominal values is not mandatory if it can be adequately demonstrated that alternative characteristics meet the requirements of the registered DDR2 DIMM application. 5. Static phase offset does not include jitter. 6. VOX is specified at the DDR DRAM clock input or test load. 7. In the frequency range of 271 - 410MHz, the min and max values for tJIT(PER) and t()DYN, and the max value for tSK(O), must not exceed the corresponding min and max values of the 160 - 270MHz range. Also, the sum of the specified values for | tJIT(PER) |, | t()DYN |, and tSK(O) must meet the requirement for t(SU), and the sum of the specified values for | t()DYN | and tSK(O) must meet the requirement for t(H).
fCK (MHz) 160 to 410 160 to 410 160 to 410 160 to 410 160 to 410 160 to 410 160 to 410 160 to 410 160 to 410 160 to 270 271 to 410 160 to 270 271 to 410 160 to 270 271 to 410 160 to 270 271 to 410 271 to 410 271 to 410
Min. 0.5 1 1.5 (VDDQ/2) -0.1 0 0 -50 -50 t()DYN(MIN) -40 tJIT(PER)MIN -75 -50 30 0
Typ.(2) 2.5 2.5
Max. 8 8 4 3 (VDDQ/2) +0.1 40 -40 50 50 t()DYN(MAX) 40 tSK(O)MAX 40 tJIT(PER)MAX 75 50 80 60 33 0.5
Unit ns ns V/ns V/ns V ps ps ps ps ps ps ps ps ps KHz %
The PLL on the CSPUA877A will meet all the above test parameters while supporting SSC synthesizers with the following parameters:
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IDTCSPUA877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
TEST CIRCUIT AND SWITCHING WAVEFORMS
VDDQ
Z = 60 L = 2.97" Z = 60 L = 2.97" GND CSPUA877A GND R = 120 GND C = 10pF VTT R = 1M C = 1pF
C = 10pF VTT
R = 1M C = 1pF SCOPE
NOTE: VTT = GND
Figure 1: Output Load Test Circuit 1
VDDQ/2
Z = 60 L = 2.97" Z = 60 L = 2.97" C = 10pF VDDQ/2 CSPUA877A VDDQ/2 C = 10pF VDDQ/2
R = 10
Z = 50 R = 50 0V
R = 10
Z = 50
R = 50 0V SCOPE
Figure 2: Output Load Test Circuit 2
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IDTCSPUA877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
TEST CIRCUIT AND SWITCHING WAVEFORMS
Yx, FBOUT Yx, FBOUT
tcycle n tjit(cc) = tcycle n
tcycle n+1 tcycle n+1
Cycle-to-Cycle jitter
CLK CLK
FBIN FBIN
t(O)n
t(O)n + 1
t(O)
=
n=N 1 N
(N is a large number of samples)
t(O)n
Static Phase Offset
Yx Yx
Yx, FBOUT Yx, FBOUT
tsk(o)
Output Skew 9
IDTCSPUA877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
TEST CIRCUIT AND SWITCHING WAVEFORMS
Yx, FBOUT Yx, FBOUT
tcycle n
Yx, FBOUT Yx, FBOUT 1 fo 1 fo
tjit(per)
NOTE: fo = Average input frequency measured at CLK / CLK
=
tcycle n
Period jitter
Yx, FBOUT Yx, FBOUT
thalf period n
Yx, FBOUT Yx, FBOUT 1 fo
thalf period n+1
tjit(hper) = thalf period n
NOTE: fo = Average input frequency measured at CLK / CLK
1 2*fo
Half-Period jitter
10
IDTCSPUA877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
TEST CIRCUIT AND SWITCHING WAVEFORMS
OE tEN 50% VDDQ Y/Y Y 50% VDDQ
Y
OE 50% VDDQ tDIS Y 50% VDDQ Y
Time Delay Between Output Enable (OE) and Clock Output (Y, Y)
CLK CLK
FBIN FBIN t(O)
SSC OFF SSC ON
t(O)
SSC OFF SSC ON
t(O)DYN
t(O)DYN
Dynamic Phase Offset
t(O)DYN
t(O)DYN
11
IDTCSPUA877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
TEST CIRCUIT AND SWITCHING WAVEFORMS
80% Clock Inputs and Outputs, OE 20% tR(I), tR(O) V80% V20% tR(I/O) tF(I), tF(O) tSLF(I/O) =
Input and Output Slew Rates
80% VID, VOD 20%
tSLR(I/O) =
V80%
V20%
tF(I/O)
VIA CARD
1
BEAD 0603
AVDD 4.7uF 1206 0.1uF 0603
VDDQ 1 10 0.1uF 0603
VDDQ
2200pF 0603 CSPUA877A
GND
VIA CARD AGND GND
NOTES: Place all decoupling capacitors as close to the CSPUA877A pins as possible. Use wide traces for AVDD and AGND. Recommended bead: Fair-rite P/N 2506036017Y0 or equivalent (0.8 DC max., 600 at 100MHz).
Recommended Filtering for the Analog and Digital Power Supplies (AVDD and VDDQ)
APPLICATION INFORMATION
Clock Loading on the PLL outputs (pF) Clock Structure #1 #2 # of SDRAM Loads per Clock 2 4 Min. 3 6 Max. 5 10
12
IDTCSPUA877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
APPLICATION INFORMATION
~2.5" ~0.6" (split to terminator)
SDRAM CSPUA877A Z = 60 CLK R = 120 CLK R = 120 Z = 60
FBIN C = 10pF R = 120 FBIN
8 more ~0.3"
SDRAM
Feedback path
Clock Structure 1
~2.5"
~0.6" (split to terminator)
SDRAM SDRAM CSPUA877A Z = 60 CLK R = 120 CLK SDRAM ~0.3" FBIN SDRAM
Stacked
R = 120 Z = 60
FBIN C = 10pF R = 120
8 more
Stacked
Feedback path
Clock Structure 2
13
IDTCSPUA877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
X XX IDTCSPUA XXXXX Device Type Package Process Blank BVG NLG 0C to +70C (Commercial) Very Fine Pitch Ball Grid Array - Green Thermally Enhanced Plastic Very Fine Pitch Quad Flat Pack No Lead Package - Green 1.8V PLL Differential 1:10 SDRAM Clock Driver
877A
CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com
for Tech Support: logichelp@idt.com
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